{"id":10979,"date":"2009-09-16T10:37:48","date_gmt":"2009-09-16T14:37:48","guid":{"rendered":"tag:www.legitreviews.com:\/\/bc8afe104b4ccdd873a5d56a86db60c6"},"modified":"2009-09-16T10:37:48","modified_gmt":"2009-09-16T14:37:48","slug":"arm-announces-2ghz-capable-cortex-a9-dual-core-processor","status":"publish","type":"post","link":"https:\/\/computerhunter.us\/?p=10979","title":{"rendered":"ARM Announces 2GHz Capable Cortex-A9 Dual Core Processor"},"content":{"rendered":"<p>Cambridge, England-based chip company ARM announced today the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. This chip is explicitly aimed at markets currently served by Intel&#39;s x86 chips and IBM&#39;s PowerPC. <center><img decoding=\"async\" src=\"http:\/\/legitreviews.com\/images\/news\/2009\/arm_cortex.jpg\" alt=\"ARM 2GHz Cortex-A9 MPCore Processor\" title=\"ARM 2GHz Cortex-A9 MPCore Processor\" \/><\/center><\/p>\n<blockquote>\n<p>In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon. The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area.  Each Cortex-A9 hard macro implementation also includes the CoreSight Program Trace Macrocell (PTM) which provides full visibility into the processors instruction flow, enabling the software community to develop code for optimal performance.<\/p>\n<\/blockquote>\n","protected":false},"excerpt":{"rendered":"<p>Cambridge, England-based chip company ARM announced today the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. This chip is explicitly aimed at markets currently served by Intel&#39;s x86 chips and IBM&#39;s PowerPC. <img decoding=\"async\" src=\"http:\/\/legitreviews.com\/images\/news\/2009\/arm_cortex.jpg\" alt=\"ARM 2GHz Cortex-A9 MPCore Processor\" \/><\/p>\n<blockquote>\n<p>In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon. The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area.  Each Cortex-A9 hard macro implementation also includes the CoreSight Program Trace Macrocell (PTM) which provides full visibility into the processors instruction flow, enabling the software community to develop code for optimal performance.<\/p>\n<\/blockquote>\n<p> <a href=\"https:\/\/computerhunter.us\/?p=10979\">Continue reading <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-10979","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/computerhunter.us\/index.php?rest_route=\/wp\/v2\/posts\/10979","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/computerhunter.us\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/computerhunter.us\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/computerhunter.us\/index.php?rest_route=\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/computerhunter.us\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=10979"}],"version-history":[{"count":0,"href":"https:\/\/computerhunter.us\/index.php?rest_route=\/wp\/v2\/posts\/10979\/revisions"}],"wp:attachment":[{"href":"https:\/\/computerhunter.us\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=10979"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/computerhunter.us\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=10979"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/computerhunter.us\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=10979"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}